Currently, with the continuous improvement of the resolution of liquid crystal display panels, particularly as for liquid crystal display panels of small dimension, the improvement of the resolution means the increase of the quantity of pixels in unit length, namely PPI (pixels per inch), and hence the quantity of leading wires within the same space increases accordingly.
It is known to the inventor that, generally, the space for wiring is reduced as much as possible by adoption of alternate wiring for an IC (integrated circuit) to solve the problem of more and more IC pins. FIG. 1 is a schematic view illustrating a gate layer and a source/drain (SD) metal layer which have wires thereof alternate with each other, 01 represents the gate layer and 02 represents the SD metal layer. The alternate wiring is performed through the gate layer and the SD metal layer, then through holes are formed in the gate layer and the SD metal layer by an exposing and etching process and finally wires are led out by an ITO (indium tin oxide) layer. The left side and the right side of FIG. 2 are respectively sectional views of the gate layer and the SD metal layer which have wires thereof alternate with each other. In FIG. 2 a gate signal access terminal includes a gate electrode 01, a gate insulating (GI) layer (03), a passivation (PVX) layer 04 and a conductive film 05 (e.g., an ITO layer) which are formed on a substrate 00 in sequence. An SD signal access terminal includes the GI layer 03, an SD metal layer 02, the PVX layer 04 and the conductive film 05 which are formed on the substrate 00 in sequence. As the gate signal access terminal (pad) and the SD signal access terminal have different structures, the finally formed signal access terminals have different heights, and hence poor contact between IC bonding pads and IC pins can be caused. As illustrated in FIG. 3, the height of the conductive film 05 in the SD signal access terminal is greater than that of the conductive film 05 in the gate signal access terminal. Height difference occurs between the conductive films 05 in the IC bonding pads corresponding to adjacent IC pins 07, and hence the contact areas between conductive balls 07 and the conductive films 05 in adjacent IC bonding pads are different and the applied forces are nonuniform. Thus, poor welding state can be caused and the conductivity can be reduced.